| 摘要 |
PURPOSE:To decrease the bus occupation frequency and to shorten the processing time in a system where the addresses of plural modules are designated, by securing a field on a common bus to designate plural modules simultaneously. CONSTITUTION:An offset field OF111 of (a) bits is secured on a common bus to designate 2<n> sets of module groups. Similarly, an m-bit address vector field 112 is secured on the common bus to select and designates simultaneously plural modules (at most m pieces) out of plural designated module groups. The high- order n-bit 31 of an address register 3 and the address of the OF111 are supplied to a comparator 4 and a coincidence signal is sent to a check circuit 6. While the low-order m-bit 32 of the register 3 opens a corresponding AND 62 out of (m) pieces of decoding signals 51 via a decoding circuit 5 to secure the input of the data set one the corresponding field 112. Then a selection signal 61 is outputted via the circuit 6. |
