| 摘要 |
PURPOSE:To control counters in common and use only one updating circuit by supplying values to be counted of the counters, update directions characteristic to the counters, addition and subtraction constants, and an address which can be scanned in common to count indication pulse signals. CONSTITUTION:An address generating circuit 3 is supplied with an address to initialize register files 1 and 2 through signal lines 6 and 10, and makes a scan in machine cycles to supply the address to files 1 and 2 and an FF group 4 through a signal line 13, and the output of the file 1 is operated by the output of the file 2 through an adder and subtracter 5 by the output indication of the FF group 4 to store the result in the file 1 again. This operation is called update. For example, when there are addresses ''0'', ''1'', and ''2'', the address ''0'' is updated in some machine cycle T0, and then the addresses ''1'' and ''2'' are updated in T0+1 and T0+2 and the address ''0'' is updated in T0+3, so that only when a signal line 15 is at ''1'', the value to be counted of the file 1 is counted. Therefore, the plural counters are constituted by only one updating circuit regardless of the difference among characteristic update conditions. |
