发明名称 DECISION CIRCUIT
摘要 PURPOSE:To eliminate a DC offset accurately by providing a switch circuit giving an output signal of a sample means to one of two output terminals in response to a control signal and using an intermediate value of the output of a voltage memory circuit connected respectively to the two output terminals as a reference signal. CONSTITUTION:A switch circuit 5 inputted a part of a sample and hold signal switches and outputs an input signal to two output terminals in response to a control signal CONT being an output of a binarization circuit 8. Then the two outputs are inputted to a voltage memory circuit comprising capacitors 6a, 6b and resistors 7a, 7b and a voltage R being a connecting point between the resistors 7a and 7b is an intermediate value of the voltage stored in the capacitors 6a, 6b and an optimum reference voltage is obtained. Then the binarization circuit 8 outputs a binary logic signal representing whether the sampled voltage by the sampled-and-hold circuit 3 is higher or lower than the reference voltage R. The binary logic signal is outputted from an output terminal 9 as a decision signal and inputted to the switch circuit 5 as a control signal CONT.
申请公布号 JPS6323413(A) 申请公布日期 1988.01.30
申请号 JP19860165572 申请日期 1986.07.16
申请人 NEC CORP 发明人 AKAIWA YOSHIHIKO
分类号 H03K5/08;H04L25/03;H04L25/06 主分类号 H03K5/08
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