发明名称 DATA BIT RATE CONVERSION CIRCUIT
摘要 <p>PURPOSE:To convert the bit rate with less hardware while keeping the state of a parallel data as it is possibly by applying bit rate conversion to a bit string different in transmission speed to an effective bit string in n-bit unit. CONSTITUTION:An incoming data is fed to a parallel application terminal 1 and stored once in a data storage memory 2. A parallel shift device 3 extracts an n-bit reconstruction data from a parallel data from the data storage memory 2 and a storage data not outputted in the preceding time. Further, a bit number counter 4 counts an effective bit in a parallel data corresponding to the transmission speed of the incoming data and the effective bit number not outputted and applies output control of normal data to the parallel shift device 3. Further, a data storage device 5 stores the storage data not outputted in the preceding time and its effective number of bits and transmits it to the parallel shift device 3 and the bit number counter 4. Thus, the bit rate is converted without converting it into a serial data so as to eliminate the need for the circuit of serial/parallel or parallel/serial convertion thereby attaining high speed operation.</p>
申请公布号 JPS6323435(A) 申请公布日期 1988.01.30
申请号 JP19860063159 申请日期 1986.03.20
申请人 FUJITSU LTD 发明人 MORITA YOSHIO
分类号 H04L7/00;H04J3/06;H04L13/08;H04L25/40;H04L29/06 主分类号 H04L7/00
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