| 摘要 |
PURPOSE:To execute an operation at a high speed by adding a register for pipeline for executing only a transfer of a result to the post-stage, by a necessary number of stages, to each computing element, when the number of stages of the pipeline required at least for each arithmetic operation. CONSTITUTION:A controlling circuit 15 is a circuit for controlling a selection of switching circuits 12-14, executes a priority decision of an output each time, selects one appropriate result and transfers it to an arithmetic operation register 16. An execution sequence designating flip-flop 17 is set in advance when it is necessary to inhibit an execution of the succeeding instruction, when an arithmetic operation exception such as an overflow, etc., has been generated. That is, it has no meaning when it is not set, but if it is set, a control of the switching circuits 12-14 by the controlling circuit 15 is varied, and a control is executed so that an output is provided from only the latest stage of each arithmetic operation system pipeline. |
