| 摘要 |
<p>PURPOSE:To avoid malfunctions of a clock switching circuit by completing the switch of input clocks against output clocks without producing any noise. CONSTITUTION:A clock switching circuit is first reset with a reset signal RE SET of H together with a selection signal DATA set at L. Under such conditions, an input clock CLK1 is outputted to an output clock CLK0. Then the signal RESET is set at L at a time point t1 to release the reset state of the switching circuit. While the signal DATA is set at H at a time point t2. Thus the signal DATA is latched at the first rise edge of the clock CLK0 at a time point t3. Then an internal selection signal A is changed to H from L; and an inverted section signal, the inverse of A is changed to L from H. Then the output Q is obtained synchronously with an clock input, the inverse of CK since the input D1 of a gate switching circuit 2 is kept at '1'. Thus the clock CLK1 does not emerge any more at the output of an AND gate 4 and the clock CLK2 does not emerge any more at the output of an AND gate 5.</p> |
