| 摘要 |
PURPOSE:To ensure the queuing control of various I/O devices with no hardware change by selecting the timing of the ready signal to be sent back to a microprocessor in response to the queuing time data set previously at a memory. CONSTITUTION:The queuing control circuit of a CPU contains a memory 1, counter circuits 2 and 3, a selector circuit 4, a gate circuit 5, and a gate group including AND gates 6-9 and an AND gate 10, etc. The different queuing time data are previously set to the memory 1 by a program in response to the characteristics of each I/O device. Then the timing is selected by said queuing time data for the ready signal to be sent back to a microprocessor. |
