发明名称 ANALYSIS METHOD FOR INTEGRATED-CIRCUIT MASK PATTERN
摘要 PURPOSE:To quickly determine a resulting value near to the true value by means of a computer for analysis of mask patterns, by reducing the patterns in an integrated circuit to determine resistances and their values. CONSTITUTION:A minimal width W4 is first extracted from a pattern 1. The pattern is then reduced to a half width of W4. A pattern W5 small in width next to W4 is then extracted. A patterning part (a, b, c, d) having a width is reduced to a half width of W5. Such operations of extraction and reduction are repeated until all the smallest widths of the patterns become zero. As regards computing resistances in the parts becoming zero in their pattern widths, the first part becoming zero, that is, the d-e part of the reduced pattern 4 is made to have a resistance expressed in Rde (fs, W4, lde). The resistances are determined in the same way. A resistance path from the contact parts 2 to 3 can be formed by connecting the determined resistances R2f, Rfg, Rgd, and Rde.
申请公布号 JPS636855(A) 申请公布日期 1988.01.12
申请号 JP19860150786 申请日期 1986.06.26
申请人 NEC CORP 发明人 SAKATA TAKESHI
分类号 H01L21/66;G01N21/88;G01N21/956;H01L21/027;H01L21/30 主分类号 H01L21/66
代理机构 代理人
主权项
地址
您可能感兴趣的专利