| 摘要 |
PURPOSE:To eliminate unnecessary state transition even variance in time exists between input signals, and to prevent chattering, or noise from the outside from generating, by latching a digital input signal with a clock signal, and waiting the transition of a state until the same state is latched in a constant period. CONSTITUTION:A digital input signal 1 is latched at a first latch circuit 2 at the leading edge of a clock signal 3, then it is changed to outputs A0 and A1. Also, it is latched at a second latch circuit 6 at the next leading edge of the clock signal 3, then it is changed to outputs B0 and B1. A third latch circuit 10 sets a coincidence signal 8, and the output of the AND circuit 9 of the clock signal 3 as the clock signal. Therefore, the output of the third latch circuit is not updated on the way of changing the digital signal, and the output of the third latch is not updated until the time of rising the clock signal 3 after completing the above change. For this reason, a synchronizing output signal transits from a state 1 to a state 4 without passing through a state 3, and simultaneous state transition can be obtained. |
