| 摘要 |
<p>PURPOSE:To transfer data at a high speed and with high efficiency by informing a CPU board having no cache memory form another CPU board having a cache memory that the cache memory is not used. CONSTITUTION:When a CPU 15 transfers data to a CPU 10, the CPU 15 stores the data in a shared memory 16 and informs the end of preparation to the CPU 10 for transfer of data to start a program which controls the discontinuation or the actuation of a cache memory 11. Thus the CPU 10 confirms an interruption to stop the actuation of the memory 11 and fetches the data A from the memory 16. Then the memory 11 is set again after the data A is fetched so that the memory 11 is actuated. A C.CPU board 9 and a subsidiary memory 13 are controlled by the board 9 and therefore no interruption is applied to a reading action carried out from the memory 13 of the CPU 10.</p> |
