| 摘要 |
PURPOSE:To constitute an arithmetic circuit for coefficient multiplication which extends output data bit length without deteriorating an arithmetic result by providing plural read-only memories for storing the arithmetic result. CONSTITUTION:The circuit consists of a terminal 11 which receives 8-bit input data, a coefficient address generating circuit 12, an output terminal 13 which outputs 12-bit output data, a bus 15 which transmits the high-order 4 bits of the input data to ROMs 16 and 17 and the low-order 4 bits to a ROM 18, ROMs 16-18 which store the arithmetic result determined by input data information and coefficient information, and a 12-bit adding circuit 19 which adds the outputs of the ROMs 16-18 together. The output of the ROM 16 represents the high- order 8 bits of the 12 bits and the sum of the outputs of ROMs 17 and 18 represent the low-order 4 bits. Consequently, 8-bit data processing is accurately expanded to 12-bit data processing. |
