发明名称 DIGITAL EXPANSION DECODING CIRCUIT
摘要 PURPOSE:To minimize an offset at each range by filling in any bit string to a low-order side blank produced by performing digital expansion with shift from a high order by a required bit length. CONSTITUTION:Digital data of 3 bits and range data enter a digital expanding circuit 3, where they are expanded digitally and outputted as 6-bit data. Since the input data has 3 bits, a blank is produced in the low order of any range in the 6-bit output. Thus, data having a required bit length is extracted from the high order of the bit string 1,000- and the blank is filled into the low-order blank. Thus, the offset in each range is made to zero and the positive and negative amplitudes are made equal, thereby eliminating a step at the range changeover point.
申请公布号 JPS59228436(A) 申请公布日期 1984.12.21
申请号 JP19830103700 申请日期 1983.06.09
申请人 MATSUSHITA DENKI SANGYO KK 发明人 EJIMA NAOKI
分类号 H03M7/50;H03M1/66;H04B14/04;(IPC1-7):H04B12/02;H03K13/24 主分类号 H03M7/50
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