Decoder.

摘要

A separate operational section for determining the degree of a polynomial is provided to increase the process speed in determining both error locator and evaluator polynomials. When a received word is decoded based on the error location found, the received word is stored in a memory (124) and corrected and output through the designation of the address. The formula @@@ sigma j alpha <i(t-1)> is derived from the error locator equation sigma (z) = @@@ sigma jz<j>, and the value of which satisfies sigma ( alpha ) = 0 is determined to increase the process speed. The decoder and the encoder share part of the hardware to make the system compact.