发明名称 ADDRESS FORMING SYSTEM
摘要 PURPOSE:To improve a substantial arithmetic processing efficiency by adding a relative address set to the address field of an instruction word to reference address data set to a register to form a memory address. CONSTITUTION:The instruction word 11 is constituted of an operation (OP) field of 8 bits and the respective address fields (OF) 1, 2, 3. A first source address to the memory is set to the OF1 and data for designating a second source address is set. Data for designating a destination address to the memory is set to the OF3. Namely, not the address itself of the memory 13 but the data of the relative address indicating the quantity of shift from a reference value is stored in the OFs 1, 2, 3. According to this address, the data stored in the memory 13 is read to a computing element 14.
申请公布号 JPS62295138(A) 申请公布日期 1987.12.22
申请号 JP19860137319 申请日期 1986.06.14
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 SEKIDO KAZUNORI
分类号 G06F9/34;G06F12/00;G06F12/02;G06F17/16 主分类号 G06F9/34
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