发明名称 |
UN SUBSISTEMA DE MEMORIA PARA USO EN UN SISTEMA QUE SE ACOPLA A UNA LINEA PRINCIPAL DE PALABRA UNICA. |
摘要 |
<p>A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of dynamic random access memory (DRAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of sequential column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the read out of a pair of words from the preselected blocks of a single stack or adjacent stacks in tandem into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out into the data registers in the same sequence providing a double fetch capability without any loss in system performance.</p> |
申请公布号 |
ES556687(D0) |
申请公布日期 |
1987.12.16 |
申请号 |
ES19870005566 |
申请日期 |
1986.06.25 |
申请人 |
HONEYWELL INFORMATION SYSTEMS INC. |
发明人 |
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分类号 |
G06F12/04;G11C5/00;G11C8/12;G11C8/18;(IPC1-7):G11C8/00;H03K19/20 |
主分类号 |
G06F12/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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