发明名称 SORT INPUT/OUTPUT SYSTEM
摘要 PURPOSE:To shorten the executing time of a sort program by deciding the number of input/output logic blocks in order to minimize the input/output frequency against an auxiliary memory device. CONSTITUTION:The record of an input file 11 is sorted in a soft phase for each amount equal to those read successively into a 1st memory 12, and are written to a 2nd memory part 13 as the sorted logic blocks 111-116. The respective logic blocks 111-116 are outputted to an auxiliary memory device 15 in the form of strings with necessary control blocks added. In a merge phase (merge processing) a selection processing means 16 decides the number of output logic blocks in order to minimize the most suitable conditions, i.e., the input/ output time to the device 15 in case the strings stored in the device 15 are merged. A merge processing means 7 reads the logic block out of each string in the device 15 with the number of input/output blocks defined as an input/ output unit. These logic blocks are stored in a first memory part 12 and merged there.
申请公布号 JPS62285130(A) 申请公布日期 1987.12.11
申请号 JP19860129600 申请日期 1986.06.03
申请人 NEC CORP 发明人 SAITOU YOSHIHIKO
分类号 G06F7/24;G06F7/36 主分类号 G06F7/24
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