发明名称 BUFFERING SYSTEM FOR PARALLEL INFERENCE MACHINE
摘要 <p>PURPOSE:To reduce the load of a network by providing element processors constituting a parallel inference machine with buffers and displaying the variable of another element processor accessed in the previously bound and unbond variables to execute buffering. CONSTITUTION:The numbers of element processors PE to be key parts and the addresses of the processors PE in a main storage device (MS) 2 are written in a buffer device (BF) 4. On the other hand, the value of a variable (bound) or undefinition of the value (unbound) is written in the BF 4 as data to be retrieved and data accessed to another PE are stored on the basis of keys. In case a CPU 1 in the PE 0 read out the value of the variable, an MSC 3 associatively retrieves the inside of the BF 4 then another PE is accessed. Only at the time of failure, a network control device (NC) 5 accesses the MSC 3 in another PE through a network 10. Consequently, the load of the network can be sharply reduced.</p>
申请公布号 JPS62284436(A) 申请公布日期 1987.12.10
申请号 JP19860127708 申请日期 1986.06.02
申请人 FUJITSU LTD 发明人 YUHARA MASANOBU;NIWA MASASHI;SATO KIMINORI
分类号 G06F15/16;G06F9/44;G06F17/30 主分类号 G06F15/16
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