| 摘要 |
PURPOSE:To prevent a CPU from the loss of synchronization with a peripheral device by completing a transfer cycle after waiting the transfer of all the contents of a buffer to a storage device when the continuity of address is lost. CONSTITUTION:When an I/O request is generated from a CPU 1-1 to a channel device 1-3, a channel control pat 1-13 starts a peripheral device 104 through an interface control part 1-12. When the continuity of input addresses is lost, an address coincidence signal SADCI is turned off and a timing control part 1-7 suppresses and controls an input data buffer storing timing signal (SSET) so that after emptying all the contents of a data buffer 1-5, the signal SSET is turned on. When the signal SSET is turned on and input data are written in the buffer 1-5, the control part 1-12 informs the completion of transaction of the input data to the device 1-4 to end the data cycle. |
