发明名称 LOGIC ANALYZER
摘要 PURPOSE:To achieve an effective analysis, by triggering a desired combination of channels when it meets desired compound requirements and is within a set range of value. CONSTITUTION:A data of a waveform inputted from a circuit terminal to be measured is latched 1a and 1b through ports A and B and the data latched 1a and 1b is written into a memory 7 synchronizing a clock signal cp. The memory contents of the memory 7 are displayed as information indicating changes in signals from channels. After latched 1a and 1b, the data is multiplexed 3, separated into up to 2n signals to edit and fed to comparators 4a and 4b as (a) input. The comparators 4a and 4b compares the input (a) with contents (b) set corresponding to a trigger condition to determine coincidence or non-coincidence and which is larger (smaller) and the results of the judgement are sent to a trigger generation circuit 5. Finally, a trigger signal S7 is generated from the circuit 5 and receiving the signal S7, a controller 6 controls the writing of data into the memory 7 according to a control signal S6 as outputted from a controller 2.
申请公布号 JPS62285067(A) 申请公布日期 1987.12.10
申请号 JP19860128478 申请日期 1986.06.03
申请人 TOSHIBA CORP 发明人 NOMURA SEIJI
分类号 G01R13/28;G01R13/20;G06F11/22 主分类号 G01R13/28
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