| 摘要 |
PURPOSE:To execute a high decision processing by a simple circuit constitution, by constituting the titled modulator so that a DSV of each channel bit is obtained from a conversion table, with respect to each input data bit, a cumulative DSV is calculated in parallel with regard to the respective coupled bits, and an optimum coupled bit can be selected by comparing and deciding them. CONSTITUTION:An Eight to Fourteen Modulation (EFM) encoder 12 has a ROM for storing a conversion table of a data bit a channel bit, and when a data bit (DATA BIT) is inputted, a channel bit of 14 bits corresponding to said bit is outputted. Also, from an output terminal of an absolute value minimum deciding part 44, a coupled bit CBT for giving the determined minimum cumulative DSV is supplied to a coupled bit inserting part 56. In this way, in accordance with the input data bit, a Digital Sum value (DSV) of the corresponding second channel bit is generated from the conversion table, and with the respective coupled bits, the cumulative DSV is calculated in parallel, and by comparing and deciding them, an optimum coupled bit can be selected, therefore, the constitution of a device can be simplified.
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