发明名称 KEY MATRIX CONTROL SYSTEM
摘要 PURPOSE:To attain the operation in an equipment B as if key entry were given from an equipment A by providing the equipment B generating/outputting a scan line designation signal, a return line designation signal and a write signal at the peripheral of the equipment A and the 1st and 2nd latch comparators. CONSTITUTION:Latch circuits 13, 15 fetch the scan line designation signal and the return line designation signal respectively synchronously with a WRT signal from the equipment B12. In this case, a data stored in the latch circuit 13 is outputted to a comparator 14 at the same time, while a data stored in the latch circuit 15 is not outputted so long as an output enable signal from the comparator 14 does not come. Then the comparator 14 compares the scan signal from the equipment A11 with the scan line designation signal from the latch circuit 13 to output the output enable signal, then the latch circuit 15 outputs the held data to the equipment A11 as a return signal.
申请公布号 JPS62282319(A) 申请公布日期 1987.12.08
申请号 JP19860126352 申请日期 1986.05.31
申请人 TOSHIBA CORP 发明人 KIYOMIYA HIROMI
分类号 G06F3/023;H03M11/20 主分类号 G06F3/023
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