发明名称 |
Buffered FET logic gate using depletion-mode MESFET's. |
摘要 |
A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (VI); and thereby a high load drivability with a low power consumption rate is realized.
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申请公布号 |
US4712023(A) |
申请公布日期 |
1987.12.08 |
申请号 |
US19860929844 |
申请日期 |
1986.11.13 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
OTSUKI, TATSUO;SHIMANO, AKIO;AOKI, HIROMITSU;AOKI, IKUKO |
分类号 |
H03K19/0185;H03K17/687;H03K19/017;H03K19/0944;H03K19/0952;(IPC1-7):H03K19/017;H03K19/094 |
主分类号 |
H03K19/0185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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