发明名称 OUTPUT BUFFER CIRCUIT
摘要 PURPOSE:To easily specify a LSI where trouble occurs by providing a means which can control the output of an output buffer circuit irrespective of a logic input. CONSTITUTION:A control voltage is applied to a terminal 11 to control the output of an output terminal 4 to logic 0 or a high-impedance state regardless of the logical state of an input terminal 5. In this case, the control voltage of the terminal is passed through a voltage clamping means 24 to control the states of a logic circuit 20 and the output buffer circuit 22.
申请公布号 JPS62280665(A) 申请公布日期 1987.12.05
申请号 JP19860124474 申请日期 1986.05.29
申请人 FUJITSU LTD 发明人 TAKAO MITSU;SAITO SEIICHI;HAYASHI TOSHINARI
分类号 H03K19/00;G01R31/28;H03K19/0175 主分类号 H03K19/00
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