| 摘要 |
A digital multiplier has recoders (30-33) for recoding the multiplier bits to form selection bits which are applied to selectors (70, 90, 100, 110) for selecting forms of the multiplicand, either the multiplicand itself or multiples of the multiplicand, the selected forms being applied to adders (85, 95, 105, 115) which produce partial products, the adders being interconnected to produce the product. Special products generators (15-17) simultaneously generate multiples of the multiplicand which are applied to the selectors. |
