发明名称 READ ONLY MEMORY
摘要 <p>PURPOSE:To attain the miniaturization and the decrease in the power consumption of a circuit by building an address decoding output circuit having a control signal output terminal to other memory in a ROM chip and programming an address decoding operation and a ROM. CONSTITUTION:The address areas [13] of a ROM 13 of a chip 1 are 0000-FFFF, and the address areas [2] of a RAM 2 to replace and assign a part thereof are 8000-80FF. In accordance with a signal CONT 1 added to a terminal 16, a decoder DEC 12 decodes 80XX and outputs a control signal CONT 2 to a terminal 15. Other RAM 2 is selected by a signal CONT 2 and written in a cell designated by address buses A7-A0 or read to a bus 4. On the other hand, a DEC 12 sends an internal control signal 14 to a ROM 13 and makes the output of the ROM 13 into an 'H'. When an address signal is except the above-mentioned, the RAM 2 is not selected, a signal 14 is also an output 0, the output 'H' of the ROM 13 is released, and the information of the ROM 13 is read on a bus 4 in accordance with address signals A15-A0 from the external part. By such constitution, a low power consumption and miniaturization can be realized.</p>
申请公布号 JPS62279598(A) 申请公布日期 1987.12.04
申请号 JP19860122862 申请日期 1986.05.28
申请人 FUJITSU LTD 发明人 RYU YASUSHI
分类号 G11C17/00;G06F12/06;G11C17/08 主分类号 G11C17/00
代理机构 代理人
主权项
地址