| 摘要 |
PURPOSE:To attain the transferring at the speed higher than the transferring speed handled by a high level data linking procedure control circuit itself by adding the external input function of a frame inspecting sequence error to a transmitting control circuit and outer-fitting a circuit to transmit a transmitting data part and a frame inspection sequence only. CONSTITUTION:(n) divided transmitting data are inputted from a bus 4a1 to a CTL (control circuit) 1a and from buses 4a2-4an to DET (data transmitting/ frame inspection sequence error detecting circuit) 2a1-2an. For example, the CTL 1a transmits the transmitting waveform of a figure (a). Respective DET 2a1, etc., receive the timing instruction of data transmitting and FCS sending from the CTL 1a through a signal line 6a and transmits transmitting data DATA2, etc., and an FSC. At the time of receiving, for example, a CTL1b obtains a flag F synchronization and receives the frame of a figure (a) from a bus 4b1. Respective DET2b1, etc., obtain the receiving timing from the CTL1b through a signal line 6b and receive the transmitting data DATA2, etc.,and the FCS. At this time, when the CTL1b removes '0', '0' removal is executed by the same timing even by the DET2b1, etc.
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