Edge detector circuit and oscillator using same

摘要

A circuit useful as an edge detector or pulse width encoder which receives an input signal and supplies a logic output signal includes a delay and inverting circuit for logically inverting and delaying input signals so as to supply a delayed and inverted signal or pulse. The circuit also includes a gate having a first input for receiving the input signal and a second input for receiving the delayed and inverted pulse. The gate provides a logic output signal whenever the input pulse signal and the delayed and inverted output pulse are at different logic levels. The circuit may be expanded with additional circuit elements including a delay circuit for delaying the input signal and an additional gate having an input for receiving the logic output signal and an output connected to the input of the delay circuit. The expanded circuit oscillates at a frequency which varies in response to the delays in the circuit. A control gate also may be included so that the logic level of a control signal determines whether the circuit oscillates.