| 摘要 |
PURPOSE:To set the shift direction of information, the order of shift and shifted bit number optionally by using an addressable latch circuit as a data storage circuit and combining it with a common information transmission line. CONSTITUTION:Information of parallel input/output lines 1c, 1d-Nc and Nd is set to latches 31-3N by using a parallel input/output control signal 1. An address signal 1i is applied during one clock period of clocks 4, 6, 5 respectively and an address signal 2i is applied during one clock period of signals 4, 6, 5 respectively. The information in the latch 31 is outputted to transmission lines 2, 3 by the signal 1i and stored in an inverter INV11 via a transfer gate TG10 by the signal 4. The information is stored in the INV13 via a TG12 by using the signal 5 and stored in an INV15 via a TG14 by using the signal 6. The said information and the information via the INV16 are sent to the lines 2, 3 via the TGs 17, 18 during a time of the signal 5 by using a control signal 7 and written in a latch 32 activated by the signal 2i. |
