发明名称 MEMORY CONTROL CIRCUIT
摘要 PURPOSE:To increase the processing speed of each processor by providing plural memory areas where data can be simultaneously written in memory banks, which have plural ports and are provided correspondingly to plural processors, by corresponding processors and data can be read out by plural processors independently of one another. CONSTITUTION:Each of memory banks 15-18 is divided into four memory blocks, and data on a write bus is simultaneously written in respective memory blocks of one memory bank on a basis of the write request signal of one processor with respect to the write processing. With respect to the read processing, read data b1-b4 from respective memory blocks in, for example, the memory bank 15 are outputted to read busses 23-26 independently of one another on a basis of read request signals of processors 7-10. Thus, each processor accesses the shared memory at a high speed to increase the processing speed of the processor.
申请公布号 JPS62272352(A) 申请公布日期 1987.11.26
申请号 JP19860116552 申请日期 1986.05.21
申请人 MATSUSHITA GRAPHIC COMMUN SYST INC 发明人 SASAKI MASAHIRO
分类号 G06F15/167;G06F12/00;G06F12/06;G06F13/18;G11C8/16 主分类号 G06F15/167
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