发明名称 |
INTERRUPTION ADDRESS GENERATING CIRCUIT |
摘要 |
PURPOSE:To attain the miniaturization of a circuit by connecting source of plural transistors (TRs) whose gates are connected in common to the highest order input signal line to drains of the TRs in common so as to decrease the occupied area of the titled circuit. CONSTITUTION:A source of TRs receiving a signal from the lowest order input signal line 3 or 6 is connected to grounding potential and its drain is connected to a source of a TR receiving a signal of the higher input signal line 2 or 5. Drains of the TRs receiving the signal from the input signal line 2 or 5 are connected in common to sources of plural TRs receiving a signal of the highest order input signal line 1 or 4 in common. The drain of each TR corresponding to the highest order input signal line 1 or 4 is connected to plural address signal lines individually or opened. The circuitry of the constitution above copes with the case of plural input signals and the increased address length.
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申请公布号 |
JPS62272719(A) |
申请公布日期 |
1987.11.26 |
申请号 |
JP19860116509 |
申请日期 |
1986.05.21 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SHIMAZU MASAKO |
分类号 |
H03K17/693;G06F9/46;G06F9/48 |
主分类号 |
H03K17/693 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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