| 摘要 |
<p>PURPOSE:To avoid disturbance of a processing program operation by resetting a digital signal processor with a stop indicating signal and restarting the program operation when a prescribed time passed after releasing the reset mode of the signal processor. CONSTITUTION:When the stop indicating signal PCNT is kept at '1', an FF-F 5 is set at '1' and the reset mode of a digital signal processing circuit A is already released. When the signal PCNT is set at '0', no pulse is hereafter given to an action clock terminal DCLK and therefore the program processing is stopped. Then the FF-F 5 is set with the 4th pulse of an internal clock CLK and the reset mode of the circuit A is released when the signal PCNT is set again at '1'. If a fixed address start signal SYNC is produced before the FF-F 5 is set after generation of the signal PCNT, an FF-F is set at '1' at the rise time point of an AND gate G3. Therefore, a G4 is kept at '0' together with the program processing kept halt. Then the program processing is restarted when the FF-F 8 is set at '0'.</p> |
