发明名称 SYNCHRONIZING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To easily understand the formation of a circuit, to facilitate the change and to reduce the IC of the circuit to lower a cost by dividing the repeating unit of a synchronizing signal into respective states to sequentially move and forming the vertical and horizontal synchronizing signals in the corresponding state. CONSTITUTION:A state change means divides the repeating unit of the synchronizing signal into the respective states of the vertical synchronizing signal 0, a vertical and horizontal conversion part 1, the horizontal synchronizing signal part 3, a horizontal/vertical conversion part 2 and respective timing signals are logically operated and the respective states are sequentially converted into other state with the pass of respective duration. At the time of converting to the state 0, a vertical synchronizing signal forming means forms the vertical synchronizing signal from the timing signal and at the time of converting to the state 3, a horizontal synchronizing signal forming means forms plural horizontal synchronizing signal pulses from the timing signal. A synchronizing signal output means logically adds the vertical synchronizing signal and the horizontal synchronizing signal to form the vertical and horizontal synchronizing signal and output.
申请公布号 JPS62266976(A) 申请公布日期 1987.11.19
申请号 JP19860110307 申请日期 1986.05.14
申请人 CSK CORP 发明人 ISHIJIMA TOMOHARU
分类号 G09G5/18;G09G1/00;G09G1/04;H04N5/067 主分类号 G09G5/18
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