| 摘要 |
PURPOSE:To shorten the time needed for the logic correction or the turnaround to the addition of a test pattern by displaying the trouble detecting signal for the produced test pattern on a display device with visual distinction, therefore eliminating a manual collation. CONSTITUTION:A CPU 1 receives an instruction for the display of an undetected area of a test pattern from a console 2 and displays automatically the signals of the trouble undetected areas within a memory device 4 on a display device 3 in different colors based on the network information as well as the trouble detection/undetection information stored in a memory device 4. That is, the trouble undetected signal of a produced test pattern within a logic circuit is displayed in a yellow color with a 1-fixed degeneration trouble display mode, in a blue color with a 0-fixed degeneration trouble display mode, and in a red color with a 0/1-fixed degeneration trouble display mode respectively. While the trouble detected signal is displayed in black in each mode. |
