| 摘要 |
PURPOSE:To facilitate program debugging including interrption processing, by employing an interruption control circuit and controlling an interruption processing start signal so as to favor the debugging. CONSTITUTION:To a signal line 17, a monitor mode signal which has a level 1 in program debugging mode is applied, and the signal has a level 0 during normal instruction execution. For the purpose, the contents of an interruption permit flag 1 and an interruption request flag 2 are ANDed by a gate 9 during the normal instruction execution, thereby starting interruprion processing. In program debugging mode, AND gates 3, 4, and 8 and an NAND gate 7 are validated. To a signal line 15, a set signal for the interruption request flag 2 is applied and to a signal line 16, a reset signal is applied. The interruption processing start control signal is invalidated by the signal of a signal 18. Further, the interruption processing start control signal is validated by the signal of a signal line 19. |
