| 摘要 |
<p>PURPOSE:To prevent the succeeding circuit from being failed by inhibiting the multiplying operation when the high level/low level period of an input pulse signal is a prescribed time or below. CONSTITUTION:When the high level period t1 and the low level period t2 of a clock signal exceed respectively four-period of a reference signal, since a FF 34 is set/reset by four-period of the reference signal after the leading/trailing of the clock signal respectively, a pulse q1 is outputted from an AND circuit 38 at the leading of a pulse p1 and a pulse q2 is outputted from an AND circuit 42 at the trailing and they are outputted as a data read clock signal. When the high level period t3 of a clock signal p2, however, is the four-period of the reference signal or below, the pulse p2 is not outputted from a shift register 31. The pulses q3, q4 are outputted from the circuit 38 at the leading of the pulses p2, p3 but no pulse is outputted from the circuit 42 at the trailing of the pulses p2,p3. That is, the multiplication of the clock is inhibited.</p> |
