| 摘要 |
PURPOSE:To prolong a reset time and to completely reset a flip flop circuit connected to a resetting circuit by outputting a control signal stopping resetting to a reset signal output circuit through a signal delay circuit. CONSTITUTION:When a power source voltage exceeds a regulated voltage Vp (time t1), a transistor Tr10 remained turned OFF. However, a Tr14 is in a ON state, a Tr15 in an OFF state and a Tr22 in an ON state. The logical level of the output point 21 of the Tr22 comes to a low level, and the FF circuit 20 is reset to initialize. In a time t2 the Tr10 is in an ON state to input a resetting stop signal to the signal delay circuit (b). The Tr14 attains an OFF state, while the Tr15 attains an ON state. The resetting stop signal is transmitted to a signal output circuit (c). In a two-staged inverter circuit the resetting stop signal is inputted to the signal output circuit (c) after a time 2td. In the signal output circuit (c) the Tr20 attains an OFF state, and the logical level of the output point 21 of the Tr22 comes to a high level in a time t3 after the time 2td since the time t2.
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