发明名称 BASIC CELL IN MASTER SLICE SYSTEM
摘要 PURPOSE:To eliminate an excess transistor by forming the a shape of a unit cell to be freely elongated laterally and longitudinally, thereby readily constructing a circuit such as an RAM or the like. CONSTITUTION:Two normal type basic cells BC, BC' are aligned in the gate length direction of the transistor interposed therein, four p-channel transistors QP5-QP8 having gate length are added in combination by two in a direction perpendicular to the gate length direction of the transistor interposed in the cell at one side of the gate width direction of the transistor interposed therein, and four n-channel transistors QN5-QN8 are similarly added in combination by two at the other side. Since the transistors QP6, QP8 and the transistors QN6, QN8 respecitively have common gates, 2-bit content can be obtained in case of constructing an RAM, and excess transistor is not produced. In case of constructing a unit cell, the cell can be freely elongated laterally and longitudinally.
申请公布号 JPS6017931(A) 申请公布日期 1985.01.29
申请号 JP19830125289 申请日期 1983.07.09
申请人 FUJITSU KK 发明人 SATOU SHINJI
分类号 H01L21/822;H01L21/82;H01L21/8238;H01L27/04;H01L27/092;H01L27/118;(IPC1-7):H01L21/82;H01L27/08 主分类号 H01L21/822
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