| 摘要 |
PURPOSE:To manufacture a high speed FET by a method wherein p layers are formed on the sidewalls of n<+>source.drain layers while n<+>layers are formed deeper than an n operation layer on the p layers to reduce the contact space with the source.drain for reducing the capacity. CONSTITUTION:An n type operation layer 12, a WN film 13, an SiO2 mask 20 are laminated on a semi-insulating GaAs substrate 11 to perform side etching by RIE using CF4+O2. After the side etching process, n<+>layers 16, 17 are formed by implanting ions deeper than the n layer 12. Next, the mask 20 is removed and Si ions are implanted to form n' layers 14 and then Be ions are implanted to form p layers on the sidewalls of n<+>layers 16, 17 and below the n' layers 14. After annealing process, AuGe made ohmic electrodes 18, 19 are formed to complete a selfalignment type GaAs-FET. The p layers 15 restrain the current from flowing through the substrate 11 holding the threshold value almost unchanged up to the gate length of 0.5mum. In such a constitution, the short channel effect can be avoided by a simple process reducing the capacity to manufacture a high speed FET. |
