| 摘要 |
PURPOSE:To reduce the space occupied by transistor elements by a method wherein selective gate is formed by laminating gate electrodes on a groove in an Si substrate through the intermediary of an insulating film. CONSTITUTION:N layers 301 and 302 are provided in a P type Si substrate 300 and a groove 303 is made by RIE. Overall surface is covered with an SiO2 film around 400Angstrom in thickness while a tunnel current conductive part around 120Angstrom in depth is formed on the N layer 301. A polysilicon 306 is deposited and patterned to form a gate of a selective transistor and a floating gate of a memory transistor. The polysilicon 306 is covered with an oxide film 307 and further covered with a control gate 308 of polysilicon to form N layers 309, 310 for completion of elements through normal interconnection process. In such a constitution, the breakdown strength between the drain 309 and the source 310 of selective transistor 312 is markedly increased. The breakdown strength depends on the groove depth and do not deteriorate, with a result of making elements finer. |
