INTEGRATED CIRCUIT THREE INPUTS BINARY ADDITION CELL WITH FAST SUM PROPAGATION

摘要

The binary adder cell is provided for summing three input binary variables A, B and C and has a sum output S and a carry output R. The cell comprises a first complemented exclusive-OR gate receiving the input variables A and B and providing an intermediate variable F1=A(+)B, a second complemented exclusive-OR gate receiving the intermediate variable F1 and the input variable C and providing the sum output S, a third complemented exclusive-OR gate receiving the input variables A and C and providing an intermediate variable F3=A(+)C and a carry generating circuit for generating the carry output R from the two intermediate variables F1 and F3 and the sum output S. The gates and the carry generating circuit are designed with MOS transistors according to the same general structure.