| 摘要 |
PURPOSE:To sample data accurately without requiring a control signal line for data transmission by putting the start bit of a data frame in code rule contradiction and transmitting a timing clock signal separately from data. CONSTITUTION:Data inputted from a terminal device or computer is converted by an interface part 401 into parallel data, which is further converted by a parallel-serial conversion part 403 into serial data. A synchronizing frame generation part 405 generates a synchronizing frame and the serial data converted by the parallel-serial conversion part 403 is converted into frame constitution form and then converted by a CMI encoding part 406 into CMI codes. A CRV addition part 407 adds CRV to the start bit in the data frame when there is circuit fault information and control information in the frame constitution. The data is sent out of a driver part 409 to a transmit data signal line 422 after being synchronized by a synchronization part 408 with a clock supplied from a timing clock signal supply part 404, and a transmission timing clock is sent out to a transmission timing clock signal 423.
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