| 摘要 |
<p>An automatic flight control system having two digital processors receives sensor data over a bit serial data bus through a serial-to-parallel converter. The converter formats the data into bytes corresponding to the data parameters from the sensors. One of the processors controls the bus timing and receives the data bytes which are simultaneously applied to an independent data storage element. An independent address sequencer provides sequential addresses to the independent data storage element at which to store sequential data bytes from the converter. After an entire data frame is stored in the independent data storage element, the second processor performs a bulk move of the data into its local data storage element. The sensors are configured in data subsystems which provide respective messages, each message containing an address identifying the subsystem. These addresses are utilized for directing the data messages to respective areas in the independent data storage element. The other processor compares addresses to determine that the data messages are not scrambled.</p> |
