发明名称 BLOCKING ADDRESSING DEVICE FOR MULTIDIMENSIONAL ARRANGEMENT
摘要 PURPOSE:To realize the blocking mapping to a one-dimensional storage space of a multidimensional arrangement, by generating a block address, and an in-block address from the sum of products of a subscript value of each dimension and a subscript size of each dimension, and from an addition of this subscript value, respectively. CONSTITUTION:In case of referring to an array element A (i, j, k), each array subscript (i), (j) and (k) is held in each register 11-13, and values which raised fractions of the quotient obtained by dividing a subscript size of the subscript (i) and (k) by 2N are held in input registers 14, 15, respectively. Also, the lower N bits of the registers 11-13 are supplied to full adders 20, 21, and an in-block address in a one-dimensional storage space which is brought to a rotational substitution in order to evade a bank collision against a reference is sent to an output register 22. On the other hand, the lower bits of the registers 11-13 are sent to multipliers 16, 17 and full adders 18, 19 and calculated with values of the input registers 14, 15, and an output of the full adder 19 is sent to the output register 22, as a block address of the one-dimensional storage space.
申请公布号 JPS62235659(A) 申请公布日期 1987.10.15
申请号 JP19860078655 申请日期 1986.04.04
申请人 NEC CORP 发明人 NISHI NAOKI
分类号 G06F12/02;G06F12/00;G06F12/08;G06F12/10 主分类号 G06F12/02
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