| 摘要 |
PURPOSE:To reduce the chip area by providing a decision circuit, a logical value subtraction circuit, a logical value adder circuit and a selection circuit so as to realize an in-chip tetral signal transmission system. CONSTITUTION:Discrimiantion circuits 11, 15 output a binary logical value '0' when a tetral input signal is logical value '0' or '1' and outputs a bianry logical value '1' when logical value '2' or '3'. The logical value adder circuit 12 outputs a tetral logical value '1' when a tetral input signal is logical value '0' and outputs a tetral logical value '2' when the tetral input signal is logical value '1'. The logical value subtraction circuit 13 outputs respectively tetral logical value '2' and '1' when the tetral input signal is logical value '3' and '2'. The selection circuit 14 outputs a signal from the circuit 12 when the output of the decision circuit 11 is a binary logical value '0' and outputs a signal from the circuit 13 when the output of the decision circuit 11 is binary logcial value '1'.
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