| 摘要 |
<p>A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches (32, 34) and additional circuitry (36) for providing an input to the second latch. Clock signal trains (A, B, C) and an extra TEST signal (44) are used to control the SRL arrangement in different modes. In a first mode, one of the outputs (30) from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true (30) and complement (38) outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.</p> |
