| 摘要 |
PURPOSE:To extract a clock even to an input data signal with various different signal speeds by providing a modulation oscillator phaselocked with an IF signal by a phase locked loop circuit and receiving jitter by a modulation signal, the 2nd mixer and a snynchronizing circuit. CONSTITUTION:An IF signal f outputted from a mixer 2 and given to a band pass filter 4 is inputted to a phase comparator 5. The signal f1 and the output signal of a VCO 7 being a component of a PLL are inputted to the other input of the phase comparator 5. A modulation signal fM is added to the output signal of the phase comaprator 5 to be a control signal of the VCO 7 and the output signal f2 of the VCO 7 is subject to phase modulation and the result is sent to a mixer 8. A local signal fL is fed to the other input of the mixer 8. The outputted signal is a clock signal subjected to phase modulation in the same frequency as the basic frequency of the input data signal fR. The signal f3 is synchronized with the input data signal fR by a syhchroniziag circuit 10 to obtain a signal f4 being the addition of jitter to the input data signal fR.
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