发明名称 DELAY LINE
摘要 PURPOSE:To constitute a delay line without using a circuit element by forming a spiral conductor pattern subjected to series connection via a through hole to the front face and the rear face of a dielectric and forming an earth conductor pattern to obtain a distributed capacitance in opposition to the conductor pattern of the front and rear faces separately to the different position in the broadwise direction of the substrate. CONSTITUTION:The spiral conductor pattern 4 and the conductor pattern 5 to obtain an inductance are formed to the upper face of the substate 1. The earth conductor pattern to obtain a distributed capacitance is formed to nearly the entire face to the upper face of the substrate 2 in opposition to the conductor patterns 4, 5 of the substrate 1. Further, the same conductor pattern as the conductor pattern 6 in the perspective shape is formed to the lower face of the substrate 2. Two spiral conductor patterns 7,8 are formed to the lower face of the substrate 3. The substrates 1-3 are laminated, through holes 9-13 are connected together to constitute. the entire delay line.
申请公布号 JPS62233913(A) 申请公布日期 1987.10.14
申请号 JP19860077262 申请日期 1986.04.03
申请人 TOKO INC 发明人 TSURUTA KENICHI
分类号 H03H7/34 主分类号 H03H7/34
代理机构 代理人
主权项
地址