发明名称 |
Arrangement for checking the parity of parity-bits containing bit groups |
摘要 |
A logic circuit for checking the parity of many bit groups simultaneously and jointly. The parity bits generated by the parity generators are interchanged crosswise, combined with the parity bits contained in the bit groups and applied to a single common output terminal. Consequently, only one specific output must be checked. The checking circuit itself is checked by inverting one of the parity generators periodically.
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申请公布号 |
US4698814(A) |
申请公布日期 |
1987.10.06 |
申请号 |
US19870009114 |
申请日期 |
1987.01.28 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
VERHEUL, HANS H.;MATENA, JAN |
分类号 |
G06F11/10;H01J37/30;H01J37/317;(IPC1-7):G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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