| 摘要 |
PURPOSE:To simplify the processing when data are transferred with a device set on a common bus by always securing coincidence between the array of memory blocks viewed from the processor bus side and the array of memories viewed from the common bus side. CONSTITUTION:The rewritable registers 10-1-10-8 set in response to memory blocks M1-M8 secure the fixed relation between the address at the side of a common bus 12 which gives accesses to the same area of a dual port memory device 2 and the address at the side of a processor bus 13. Then the comparators 9-1-9-8 judge a specific memory block that received an access based on the block numbers stored in the registers 10-1-10-8 and high-order N bits of the address given from the bus 12 or 13. While comparators 5-1-5-8 judges a specific memory block that received an access based on the new block numbers produced by adders 6-1-6-8 and high-order N bits of an address. Based on these results of judgement, an access is given to the device 2. |
