| 摘要 |
PURPOSE:To execute the processing based on a PQ correction logic with high efficiency and at the same time to simplify a PQ correcting circuit, by extracting the PQ correcting data words of P and Q series related to the data word given from an RAM and synchronously with a basic clock. CONSTITUTION:An error word address input/output circuit 11 extracts a relevant address out of an address bus 4 of an RAM1 by an error detecting signal I4 and sends the address to the bus 4 again by a correction command signal I3. A parity calculating circuit 12 fetches the PQ correcting data words in parallel to an FF19 from a data bus 8 synchronously with a clock pulse and then calculates the parities of both P and Q seties by means of an exclusive OR circuit 24 and an FF25. An error word extracting circuit 13 extracts an error word out of the bus 8 in response to the signal I4 and sends it to a correcting circuit 14. The circuit 14 performs a correction with addition of the error data word in case the total sum of the parity calculation results is not equal to zero. A control circuit 15 stores the corrected data word and then transmits it to the bus 8 in accordance with the signal I3. |
